RISC-V: Add testcases for scalar unsigned SAT_ADD form 3

RISC-V: Add testcases for scalar unsigned SAT_ADD form 3

After the middle-end support the form 3 of unsigned SAT_ADD and
the RISC-V backend implement the scalar .SAT_ADD, add more test
case to cover the form 3 of unsigned .SAT_ADD.

Form 3:
  #define SAT_ADD_U_3(T) \
  T sat_add_u_3_##T (T x, T y) \
  { \
    T ret; \
    return __builtin_add_overflow (x, y, &ret) ? -1 : ret; \
  }

Passed the rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat_arith.h: Add test macro for form 3.
	* gcc.target/riscv/sat_u_add-13.c: New test.
	* gcc.target/riscv/sat_u_add-14.c: New test.
	* gcc.target/riscv/sat_u_add-15.c: New test.
	* gcc.target/riscv/sat_u_add-16.c: New test.
	* gcc.target/riscv/sat_u_add-run-13.c: New test.
	* gcc.target/riscv/sat_u_add-run-14.c: New test.
	* gcc.target/riscv/sat_u_add-run-15.c: New test.
	* gcc.target/riscv/sat_u_add-run-16.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>