RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4

RISC-V: Cover sign-extensions in lshr<GPR:mode>3_zero_extend_4

The lshr<GPR:mode>3_zero_extend_4 pattern targets bit extraction
with zero-extension. This pattern represents the canonical form
of zero-extensions of a logical right shift.

The same optimization can be applied to sign-extensions.
Given the two optimizations are so similar, this patch converts
the existing one to also cover the sign-extension case as well.

gcc/ChangeLog:

	* config/riscv/iterators.md (ashiftrt): New code attribute
	'extract_shift' and adding extractions to optab.
	* config/riscv/riscv.md (*lshr<GPR:mode>3_zero_extend_4): Rename to...
	(*<any_extract:optab><GPR:mode>3):...this and add support for
	sign-extensions.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/extend-shift-helpers.h: Add helpers for
	sign-extension.
	* gcc.target/riscv/sign-extend-rshift-32.c: New test.
	* gcc.target/riscv/sign-extend-rshift-64.c: New test.
	* gcc.target/riscv/sign-extend-rshift.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>