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target/riscv: Simplify check for Zve32f and Zve64f
authorWeiwei Li <liweiwei@iscas.ac.cn>
Wed, 15 Feb 2023 02:05:33 +0000 (10:05 +0800)
committerPalmer Dabbelt <palmer@rivosinc.com>
Wed, 1 Mar 2023 23:17:51 +0000 (15:17 -0800)
commit3f4a5a5314b1d2d1fe910b87a3784743993003da
treee893e0fc71a20e6756837682d19e9db87d40acc7tree | snapshot
parent51f33081efd4cf3182bf905096888861814522a7commit | diff
target/riscv: Simplify check for Zve32f and Zve64f

V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230215020539.4788-9-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
target/riscv/cpu_helper.c diff | blob | blame | history
target/riscv/csr.c diff | blob | blame | history
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git