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(parent: d539a42) | patch
[riscv] Ensure coherent DMA allocations do not cross cacheline boundaries
authorMichael Brown <mcb30@ipxe.org>
Fri, 11 Jul 2025 12:50:41 +0000 (13:50 +0100)
committerMichael Brown <mcb30@ipxe.org>
Fri, 11 Jul 2025 12:50:41 +0000 (13:50 +0100)
commit434462a93ebe462cbd334cbf3431ff9c5b5a1aae
treeb4af12d552bdc1530f4bb2ff07f1d1ac2442bc71tree | snapshot
parentd539a420df919b3f9b808703b5f8d62bc485fe15commit | diff
[riscv] Ensure coherent DMA allocations do not cross cacheline boundaries

Signed-off-by: Michael Brown <mcb30@ipxe.org>
src/arch/riscv/core/riscv_dma.c diff | blob | blame | history
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