target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-10-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
(cherry picked from commit db21c3eb05504c4cedaad4f7b19e588361b02385)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>