RISC-V: Make vector strided store alias all other memories

RISC-V: Make vector strided store alias all other memories

Almost the same as the RVV strided load, the vector strided store
doesn't involve the (mem:BLK (scratch)) to alias all other memories.
It will make the alias analysis only consider the base address of
strided store.

	PR target/118075

gcc/ChangeLog:

	* config/riscv/vector.md: Add the (mem:BLK (scratch)) as the
	lhs of strided store define insn.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr118075-run-1.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>