RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1.

RISC-V:Add testcases for signed .SAT_ADD IMM form 1 with IMM = -1.

This patch adds testcase for form1, as shown below:

T __attribute__((noinline))                  \
sat_s_add_imm_##T##_fmt_1##_##INDEX (T x)             \
{                                            \
  T sum = (UT)x + (UT)IMM;                     \
  return (x ^ IMM) < 0                         \
    ? sum                                    \
    : (sum ^ x) >= 0                         \
      ? sum                                  \
      : x < 0 ? MIN : MAX;                   \
}

Passed the rv64gcv regression test.

Signed-off-by: Li Xu <xuli1@eswincomputing.com>
gcc/testsuite/ChangeLog:

	* gcc.target/riscv/sat/sat_s_add_imm-2.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1-i16.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-3.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1-i32.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-4.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1-i64.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-1-i8.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-run-2.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-1-i16.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-run-3.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-1-i32.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-run-4.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-1-i64.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-run-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm-run-1-i8.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-2-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i16.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-3-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i32.c: ...here.
	* gcc.target/riscv/sat/sat_s_add_imm-1-1.c: Move to...
	* gcc.target/riscv/sat/sat_s_add_imm_type_check-1-i8.c: ...here.