]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Tue, 10 Oct 2023 01:39:04 +0000 (09:39 +0800)
committerLehua Ding <lehua.ding@rivai.ai>
Tue, 10 Oct 2023 10:23:40 +0000 (18:23 +0800)
commit4d230493f57dd11b8de9155b03088092f2ecea5c
tree5b0185d3544aa777f9aca0ac29ed93004d0a0f79
parentaaa5a5318adbefe87c1b781b8a3e5fc332e661ec
RISC-V Regression: Fix FAIL of bb-slp-pr65935.c for RVV

Here is the reference comparing dump IR between ARM SVE and RVV.

https://godbolt.org/z/zqess8Gss

We can see RVV has one more dump IR:
optimized: basic block part vectorized using 128 byte vectors
since RVV has 1024 bit vectors.

The codegen is reasonable good.

However, I saw GCN also has 1024 bit vector.
This patch may cause this case FAIL in GCN port ?

Hi, GCN folk, could you check this patch in GCN port for me ?

gcc/testsuite/ChangeLog:

* gcc.dg/vect/bb-slp-pr65935.c: Add vect1024 variant.
* lib/target-supports.exp: Ditto.
gcc/testsuite/gcc.dg/vect/bb-slp-pr65935.c
gcc/testsuite/lib/target-supports.exp