]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: convert abstract CPU classes to RISCVCPUDef
authorPaolo Bonzini <pbonzini@redhat.com>
Thu, 6 Feb 2025 16:03:01 +0000 (17:03 +0100)
committerPaolo Bonzini <pbonzini@redhat.com>
Tue, 20 May 2025 06:18:53 +0000 (08:18 +0200)
commit4e012d36c8654e7fa12762002150334bf591628a
tree32da0de09daab115fd01b0690472a44d510007d4
parenta6ba81424a7e751fbcee40dc1f5826ba29fddd30
target/riscv: convert abstract CPU classes to RISCVCPUDef

Start from the top of the hierarchy: dynamic and vendor CPUs are just
markers, whereas bare CPUs can have their instance_init function
replaced by RISCVCPUDef.

The only difference is that the maximum supported SATP mode has to
be specified separately for 32-bit and 64-bit modes.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/riscv/cpu.c
target/riscv/cpu.h