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(parent: de04f73) | patch
Refine predicate of operands[2] in divv4hf3 with register_operand.
authorliuhongt <hongtao.liu@intel.com>
Tue, 10 Oct 2023 03:32:09 +0000 (11:32 +0800)
committerliuhongt <hongtao.liu@intel.com>
Wed, 11 Oct 2023 04:58:17 +0000 (12:58 +0800)
commit4efe9085d087a8d94261e4c38dd2ba840f3419ac
tree79d811974a845b49a61a3d8d3e5d3b17c4d81f4atree
parentde04f73eefd856914f4a253ad2f1579239512e31commit | diff
Refine predicate of operands[2] in divv4hf3 with register_operand.

In the expander, it will emit below insn.

rtx tmp = gen_rtx_VEC_CONCAT (V4SFmode, operands[2],
force_reg (V2SFmode, CONST1_RTX (V2SFmode)));

but *vec_concat<mode> only allow register_operand.

gcc/ChangeLog:

PR target/111745
* config/i386/mmx.md (divv4hf3): Refine predicate of
operands[2] with register_operand.

gcc/testsuite/ChangeLog:

* gcc.target/i386/pr111745.c: New test.
gcc/config/i386/mmx.md diff | blob | blame | history
gcc/testsuite/gcc.target/i386/pr111745.c [new file with mode: 0644] blob
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