]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Remove unnecessary option for scalar SAT_SUB testcase
authorPan Li <pan2.li@intel.com>
Sat, 16 Nov 2024 00:31:56 +0000 (08:31 +0800)
committerPan Li <pan2.li@intel.com>
Sat, 16 Nov 2024 00:34:49 +0000 (08:34 +0800)
commit4f9af8e4d123d222fa5f83ad0581ca2fe96e7269
tree3bd98712e1262b1a3d79d8fd19393ac78d7a245b
parent349368aeba4b4a7e7bc6c1c188d4759e63af2c66
RISC-V: Remove unnecessary option for scalar SAT_SUB testcase

After we create a isolated folder to hold all SAT scalar test,
we have fully control of what optimization options passing to
the testcase.  Thus, it is better to remove the unnecessary
work around for flto option, as well as the -O3 option for
each cases.  The riscv.exp will pass sorts of different optimization
options for each case.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/sat/sat_u_sub-1-u16.c: Remove flto dg-skip
workaround and -O3 option.
* gcc.target/riscv/sat/sat_u_sub-1-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-1-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-1-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-10-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-10-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-10-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-10-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-11-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-11-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-11-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-11-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-12-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-12-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-12-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-12-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-2-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-2-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-2-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-2-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-3-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-3-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-3-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-3-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-4-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-4-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-4-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-4-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-5-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-5-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-5-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-5-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-6-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-6-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-6-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-6-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-7-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-7-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-7-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-7-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-8-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-8-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-8-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-8-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-9-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-9-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-9-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub-9-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c: Ditto.
* gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>
100 files changed:
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-1-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-10-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-11-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-12-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-2-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-3-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-4-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-5-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-6-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-7-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-8-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub-9-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-3.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16-4.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-3.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32-4.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-3.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8-4.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-1-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16-3.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32-3.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8-3.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-2-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-3-u8.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u16.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u32.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u64.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-1.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8-2.c
gcc/testsuite/gcc.target/riscv/sat/sat_u_sub_imm-4-u8.c