]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add vmin.vx C API tests
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Fri, 3 Feb 2023 07:20:38 +0000 (15:20 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Fri, 10 Feb 2023 11:27:04 +0000 (19:27 +0800)
commit5255664d4ab144b35d93d67e2251b79f21d817ad
treeb146fd4adea25cee269f438ebfb39ffdec5e5636
parentf82338eca2f754b55512bbf67a6f08e45eaa56ae
RISC-V: Add vmin.vx C API tests

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/vmin_vx_m_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_m_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_m_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_m_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_m_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_m_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tumu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tumu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tumu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tumu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tumu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vmin_vx_tumu_rv64-3.c: New test.
36 files changed:
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv32-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv32-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv32-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv64-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv64-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_m_rv64-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv32-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv32-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv32-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv64-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv64-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_rv64-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv32-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv32-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv32-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv64-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv64-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vx_tumu_rv64-3.c [new file with mode: 0644]