]> git.ipfire.org Git - thirdparty/qemu.git/commit
hw/intc/loongarch_pch: Discard write operation with ISR register
authorBibo Mao <maobibo@loongson.cn>
Wed, 7 May 2025 02:31:38 +0000 (10:31 +0800)
committerSong Gao <gaosong@loongson.cn>
Wed, 14 May 2025 07:46:08 +0000 (15:46 +0800)
commit53339a8120d9be6a448f29dd1138bab2fa15e34d
tree5ed505386f4d9253315ff86f06322c1c97d2ba81
parentab3ab67348b1e34630272b05f9f7f187fd6a1f8f
hw/intc/loongarch_pch: Discard write operation with ISR register

With the latest 7A1000 user manual, interrupt status register ISR is
read only. Here discard write operation with ISR register.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20250507023148.1877287-7-maobibo@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
hw/intc/loongarch_pch_pic.c