]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add RVV registers register spilling
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Sun, 6 Nov 2022 08:56:33 +0000 (16:56 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Fri, 11 Nov 2022 08:16:13 +0000 (00:16 -0800)
commit5576518a5667ad826937125a19b7c59c34d8733c
tree1ed21ca1b776c24f97651aad2145733b05e2b70a
parentfbad7a74aaaddea3d7b39045a09dd3860603658e
RISC-V: Add RVV registers register spilling

This patch support RVV scalable register spilling.
prologue && epilogue handling pick up prototype from Monk Chiang <monk.chiang@sifive.com>.
Co-authored-by: Monk Chiang <monk.chiang@sifive.com>
gcc/ChangeLog:

* config/riscv/riscv-v.cc (emit_pred_move): Adjust for scalable register spilling.
(legitimize_move): Ditto.
* config/riscv/riscv.cc (riscv_v_adjust_scalable_frame): New function.
(riscv_first_stack_step): Adjust for scalable register spilling.
(riscv_expand_prologue): Ditto.
(riscv_expand_epilogue): Ditto.
(riscv_dwarf_poly_indeterminate_value): New function.
(TARGET_DWARF_POLY_INDETERMINATE_VALUE): New target hook support for register spilling.
* config/riscv/riscv.h (RISCV_DWARF_VLENB): New macro.
(RISCV_PROLOGUE_TEMP2_REGNUM): Ditto.
(RISCV_PROLOGUE_TEMP2): Ditto.
* config/riscv/vector-iterators.md: New iterators.
* config/riscv/vector.md (*mov<mode>): Fix it for register spilling.
(*mov<mode>_whole): New pattern.
(*mov<mode>_fract): New pattern.
(@pred_mov<mode>): Fix it for register spilling.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/macro.h: New test.
* gcc.target/riscv/rvv/base/spill-1.c: New test.
* gcc.target/riscv/rvv/base/spill-10.c: New test.
* gcc.target/riscv/rvv/base/spill-11.c: New test.
* gcc.target/riscv/rvv/base/spill-12.c: New test.
* gcc.target/riscv/rvv/base/spill-2.c: New test.
* gcc.target/riscv/rvv/base/spill-3.c: New test.
* gcc.target/riscv/rvv/base/spill-4.c: New test.
* gcc.target/riscv/rvv/base/spill-5.c: New test.
* gcc.target/riscv/rvv/base/spill-6.c: New test.
* gcc.target/riscv/rvv/base/spill-7.c: New test.
* gcc.target/riscv/rvv/base/spill-8.c: New test.
* gcc.target/riscv/rvv/base/spill-9.c: New test.
18 files changed:
gcc/config/riscv/riscv-v.cc
gcc/config/riscv/riscv.cc
gcc/config/riscv/riscv.h
gcc/config/riscv/vector-iterators.md
gcc/config/riscv/vector.md
gcc/testsuite/gcc.target/riscv/rvv/base/macro.h [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-12.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-4.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-5.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-6.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-7.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-8.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c [new file with mode: 0644]