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(parent: 7803ec5) | patch
aarch64: Force TImode values into even registers
authorRichard Henderson <richard.henderson@linaro.org>
Wed, 31 Oct 2018 10:00:45 +0000 (10:00 +0000)
committerRichard Henderson <rth@gcc.gnu.org>
Wed, 31 Oct 2018 10:00:45 +0000 (03:00 -0700)
commit563cc649beaf11d707c422e5f4e9e5cdacb818c3
treea4713d9eebef54bd572c5cbdd5238258187f98b8tree | snapshot
parent7803ec5ee2a547043fb6708a08ddb1361ba91202commit | diff
aarch64: Force TImode values into even registers

The LSE CASP instruction requires values to be placed in even
register pairs.  A solution involving two additional register
classes was rejected in favor of the much simpler solution of
simply requiring all TImode values to be aligned.

* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
16-byte modes held in GP registers to use an even regno.

From-SVN: r265661
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