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MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
authorThomas Bogendoerfer <tsbogend@alpha.franken.de>
Mon, 14 Sep 2020 16:05:00 +0000 (18:05 +0200)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Tue, 15 Sep 2020 08:40:29 +0000 (10:40 +0200)
commit564c836fd945a94b5dd46597d6b7adb464092650
tree1c8500388f9aada05ebd9958f2b26b30c72b132ftree | snapshot
parentbaf5cb30fbd1c22f6aa03c081794c2ee0f5be4dacommit | diff
MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT

Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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