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(parent: 1277bac) | patch
arm: vf610: add DDR_SEL_PAD_CONTR register
authorStefan Agner <stefan@agner.ch>
Wed, 23 Apr 2014 16:17:51 +0000 (18:17 +0200)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Sun, 25 May 2014 13:46:12 +0000 (15:46 +0200)
commit56d83d1c046c693b65ab09c0e960d922ec639c2b
tree87c48bc6742a97768be857d92f18976665d3feeftree | snapshot
parent1277bac0d21bfa6952bdb14fcbf4134aa3018056commit | diff
arm: vf610: add DDR_SEL_PAD_CONTR register

Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM
issues with newer silicon (1.1). This register was added in revision
4 of the Vybrid Reference Manual.

Signed-off-by: Stefan Agner <stefan@agner.ch>
arch/arm/include/asm/arch-vf610/imx-regs.h diff | blob | blame | history
board/freescale/vf610twr/vf610twr.c diff | blob | blame | history
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