RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

RISC-V: unrecognizable insn ICE in xtheadvector/pr114194.c on 32bit targets

This is a follow-up to the patch below to avoid generating unrecognized
vsetivl instructions for XTheadVector.

https://gcc.gnu.org/pipermail/gcc-patches/2025-January/674185.html

	PR target/118601

gcc/ChangeLog:

	* config/riscv/riscv-string.cc (expand_block_move): Check with new
	constraint 'vl' instead of 'K'.
	(expand_vec_setmem): Likewise.
	(expand_vec_cmpmem): Likewise.
	* config/riscv/riscv-v.cc (force_vector_length_operand): Likewise.
	(expand_load_store): Likewise.
	(expand_strided_load): Likewise.
	(expand_strided_store): Likewise.
	(expand_lanes_load_store): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/xtheadvector/pr114194.c: Move to...
	* gcc.target/riscv/rvv/xtheadvector/pr114194-rv64.c: ...here.
	* gcc.target/riscv/rvv/xtheadvector/pr114194-rv32.c: New test.
	* gcc.target/riscv/rvv/xtheadvector/pr118601.c: New test.

Reported-by: Edwin Lu <ewlu@rivosinc.com>