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target-mips: CP0 Random register improvements
authoraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Thu, 8 Jan 2009 18:48:12 +0000 (18:48 +0000)
committeraurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162>
Thu, 8 Jan 2009 18:48:12 +0000 (18:48 +0000)
commit59d9413094d7295d74926e63d7df4963399ab53a
tree4faf65e799aba0e3fcd1b0b654712615711aa2e6tree | snapshot
parent0516ede089e23f8434b6bf3294e5ccf30f5d5549commit | diff
target-mips: CP0 Random register improvements

- Use a LFSR to generate the random value
- Make sure to not return the same value twice

Based on a patch by Hervé Poussineau.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6233 c046a42c-6fe2-441c-8c8c-71466251a162
hw/mips_timer.c diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git