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(parent: 5106b8e) | patch
target/riscv: convert SiFive U models to RISCVCPUDef
authorPaolo Bonzini <pbonzini@redhat.com>
Tue, 18 Feb 2025 12:05:25 +0000 (13:05 +0100)
committerPaolo Bonzini <pbonzini@redhat.com>
Tue, 20 May 2025 06:18:53 +0000 (08:18 +0200)
commit5a62948c91a910de4f9c7332cf8803152c099eac
tree0001e711f504667e2a34d544f61ea43181d8444ftree
parent5106b8ee9ac78505f872a956c931c1f965ad073ecommit | diff
target/riscv: convert SiFive U models to RISCVCPUDef

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
target/riscv/cpu-qom.h diff | blob | blame | history
target/riscv/cpu.c diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git