RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr

RISC-V: Avoid vaaddu.vx combine pattern pollute VXRM csr

The vaaddu.vx combine almost comes from avg_floor, it will
requires the vxrm to be RDN.  But not all vaaddu.vx should
depends on the RDN.  The vaaddu.vx combine should leverage
the VXRM value as is instead of pollute them all to RDN.

This patch would like to fix this and set it as is.

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*uavg_floor_vx_<mode>): Rename
	from...
	(*<sat_op_v_vdup>_vx_<mode>): Rename to...
	(*<sat_op_vdup_v>_vx_<mode>): Rename to...
	* config/riscv/riscv-protos.h (enum insn_flags): Add vxrm
	RNE, ROD type.
	(enum insn_type): Add RNE_P, ROD_P type.
	(expand_vx_binary_vxrm_vec_vec_dup): Add new func decl.
	(expand_vx_binary_vxrm_vec_dup_vec): Ditto.
	* config/riscv/riscv-v.cc (get_insn_type_by_vxrm_val): Add
	helper to get insn type by vxrm value.
	(expand_vx_binary_vxrm_vec_vec_dup): Add new func impl
	to expand vec + vec_dup pattern.
	(expand_vx_binary_vxrm_vec_dup_vec): Ditto but for
	vec_dup + vec pattern.
	* config/riscv/vector-iterators.md: Add helper iterator
	for sat vx combine.

Signed-off-by: Pan Li <pan2.li@intel.com>