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(parent: 448e42f) | patch
target/arm: Fix cacheattr in get_phys_addr_disabled
authorRichard Henderson <richard.henderson@linaro.org>
Sat, 1 Oct 2022 16:22:55 +0000 (09:22 -0700)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 10 Oct 2022 13:52:25 +0000 (14:52 +0100)
commit5b74f9b4ed9033dc5427cd69f5ee37e7b726ecfd
tree44eb39c536742a9b697754dba2f12e5151a628c7tree
parent448e42fdc1013b3497c9a6902f8052488fc8af1acommit | diff
target/arm: Fix cacheattr in get_phys_addr_disabled

Do not apply memattr or shareability for Stage2 translations.
Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the
pseudocode in AArch64.S1DisabledOutput.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221001162318.153420-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/ptw.c diff | blob | blame | history
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