aarch64: Fix up bfmlal lane pattern [PR104921]

aarch64: Fix up bfmlal lane pattern [PR104921]

As the testcase shows, this pattern had an incorrect constraint leading
to GCC's output getting rejected by the assembler.

This patch fixes the constraint accordingly.

The test is split into two: one that can run without bf16 support from
the assembler and another that checks that the output actually assembles
when such support is available.

gcc/ChangeLog:

	PR target/104921
	* config/aarch64/aarch64-simd.md (aarch64_bfmlal<bt>_lane<q>v4sf):
	Use correct constraint for operand 3.

gcc/testsuite/ChangeLog:

	PR target/104921
	* gcc.target/aarch64/pr104921-1.c: New test.
	* gcc.target/aarch64/pr104921-2.c: New test.
	* gcc.target/aarch64/pr104921.x: Include file for new tests.

(cherry picked from commit 277e1f30a5e4e634304a7b8a532825119f0ea47f)