riscv: thead: Add support for the XTheadFMemIdx ISA extension

riscv: thead: Add support for the XTheadFMemIdx ISA extension

The XTheadFMemIdx ISA extension provides additional load and store
instructions for floating-point registers with new addressing modes.

The following memory accesses types are supported:
* load/store: [w,d] (single-precision FP, double-precision FP)

The following addressing modes are supported:
* register offset with additional immediate offset (4 instructions):
  flr<type>, fsr<type>
* zero-extended register offset with additional immediate offset
  (4 instructions): flur<type>, fsur<type>

These addressing modes are also part of the similar XTheadMemIdx
ISA extension support, whose code is reused and extended to support
floating-point registers.

One challenge that this patch needs to solve are GP registers in FP-mode
(e.g. "(reg:DF a2)"), which cannot be handled by the XTheadFMemIdx
instructions. Such registers are the result of independent
optimizations, which can happen after register allocation.
This patch uses a simple but efficient method to address this:
add a dependency for XTheadMemIdx to XTheadFMemIdx optimizations.
This allows to use the instructions from XTheadMemIdx in case
of such registers.

The added tests ensure that this feature won't regress without notice.
Testing: GCC regression test suite and SPEC CPU 2017 intrate (base&peak).

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_index_reg_class):
	Return GR_REGS for XTheadFMemIdx.
	(riscv_regno_ok_for_index_p): Add support for XTheadFMemIdx.
	* config/riscv/riscv.h (HARDFP_REG_P): New macro.
	* config/riscv/thead.cc (is_fmemidx_mode): New function.
	(th_memidx_classify_address_index): Add support for XTheadFMemIdx.
	(th_fmemidx_output_index): New function.
	(th_output_move): Add support for XTheadFMemIdx.
	* config/riscv/thead.md (TH_M_ANYF): New mode iterator.
	(TH_M_NOEXTF): Likewise.
	(*th_fmemidx_movsf_hardfloat): New INSN.
	(*th_fmemidx_movdf_hardfloat_rv64): Likewise.
	(*th_fmemidx_I_a): Likewise.
	(*th_fmemidx_I_c): Likewise.
	(*th_fmemidx_US_a): Likewise.
	(*th_fmemidx_US_c): Likewise.
	(*th_fmemidx_UZ_a): Likewise.
	(*th_fmemidx_UZ_c): Likewise.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/xtheadfmemidx-index-update.c: New test.
	* gcc.target/riscv/xtheadfmemidx-index-xtheadbb-update.c: New test.
	* gcc.target/riscv/xtheadfmemidx-index-xtheadbb.c: New test.
	* gcc.target/riscv/xtheadfmemidx-index.c: New test.
	* gcc.target/riscv/xtheadfmemidx-uindex-update.c: New test.
	* gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb-update.c: New test.
	* gcc.target/riscv/xtheadfmemidx-uindex-xtheadbb.c: New test.
	* gcc.target/riscv/xtheadfmemidx-uindex.c: New test.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>