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(parent: 37a011e) | patch
intc/xilinx_intc: Don't clear level sens. IRQs without ACK
authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>
Tue, 11 Jun 2013 00:58:25 +0000 (10:58 +1000)
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>
Tue, 18 Jun 2013 07:44:59 +0000 (09:44 +0200)
commit6327c221fff955ee979559ec85c148963e06d78f
tree87ce0cab3518107edc7d831ad0eec767bc50bd1ctree | snapshot
parent37a011e9bade7bcbdd41addffc7c94cbf628404ccommit | diff
intc/xilinx_intc: Don't clear level sens. IRQs without ACK

For level sensitive interrupts, ISR bits are cleared when the input pin
is lowered. This is incorrect. Only software can clear ISR bits (via
IAR or direct write to ISR with !MER(2)).

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
hw/intc/xilinx_intc.c diff | blob | blame | history
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