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(parent: 83441e7) | patch
RISC-V: Add VLS unary combine patterns
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Sat, 23 Sep 2023 01:44:38 +0000 (09:44 +0800)
committerPan Li <pan2.li@intel.com>
Sat, 23 Sep 2023 01:46:52 +0000 (09:46 +0800)
commit648347be1fdaaeb866607dbac02fba97d62b839b
treea711561f1402b5757e5e9e13085f701111b7285atree | snapshot
parent83441e756734cd86b017e73a396ad8a0155a1bd1commit | diff
RISC-V: Add VLS unary combine patterns

gcc/ChangeLog:

* config/riscv/autovec-opt.md: Add VLS modes for conditional ABS/SQRT.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c: New test.
gcc/config/riscv/autovec-opt.md diff | blob | blame | history
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_abs-1.c [new file with mode: 0644] blob
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/cond_sqrt-1.c [new file with mode: 0644] blob
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