[RISC-V][PR target/118122] Fix modes in recently added risc-v pattern

[RISC-V][PR target/118122] Fix modes in recently added risc-v pattern

The new pattern to optimize certain code sequences on RISC-V played things a
bit fast and loose with modes -- some operands were using the ALLI iterator
while the scratch used X and the split codegen used X.

Naturally under the "right" circumstances this would trigger an ICE due to
mismatched modes.  This patch uses X consistently in that pattern. It also
fixes some formatting nits.

Tested in my tester, but waiting on the pre-commit verdict before moving
forward.

	PR target/118122
gcc/
	* config/riscv/riscv.md (lui_constraint<X:mode>_and_to_or): Use
	X iterator rather than ANYI consistently.  Fix formatting.

gcc/testsuite

	* gcc.target/riscv/pr118122.c: New test.