[PR target/118248] Avoid bogus alloca call in RISC-V backend

[PR target/118248] Avoid bogus alloca call in RISC-V backend

This is Jakub's patch and Ian's testcase for the slightly vexing fault building
the D runtime with an s390x-x-riscv cross compiler.

The core issue is we're allocating a vector to hold temporary registers
unconditionally, including cases where the vector isn't needed because the loop
isn't going to iterate.

In the cases where the vector isn't needed the length is computed with an
expression (x / y) - 1 where x / y will be zero.  The alloca(-1) on the s390
platform triggers a fault.  We haven't seen the fault with an x86 cross, but we
can certainly see the bogus value being passed to alloca with a debugger.

Jakub patch just conditionalizes the whole block in a sensible way.  So it
looks larger than it really is.  I thought it might be better to do a bit of
manual CSE on this code to make it even more obvious, but I think we're
ultimately OK here.

Ian provided the testcase, collapsed down into equivalent C code. Again, it
doesn't fault on an x86-x-riscv, but I can see the incorrect behavior with a
debugger.

And a shout-out to Stefan for providing a docker based reproducer, it really
helped track this down.

	PR target/118248
gcc/
	* config/riscv/riscv-string.cc (riscv_block_move_straight): Only
	allocate REGS buffer if it will be needed.

gcc/testsuite
	* gcc.target/riscv/pr118248.c: New test.