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PR target/78862
authorwalt <walt@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 3 Feb 2017 18:41:57 +0000 (18:41 +0000)
committerwalt <walt@138bc75d-0d04-0410-961f-82ee72b054a4>
Fri, 3 Feb 2017 18:41:57 +0000 (18:41 +0000)
commit6a1eedf12fe1a800c7326df2eb43769ef51d4e71
treeee31af49185c9ceec99bcc3ee41eddd3a7825aeftree
parente4a330c44c2b2b9dc22fc5036adb0ec6976a81cccommit | diff
PR target/78862
* config/tilegx/tilegx.md (tilegx_expand_prologue): Add blockage
after initial stackframe link reg save.
* config/tilepro/tilepro.md (tilepro_expand_prologue): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@245159 138bc75d-0d04-0410-961f-82ee72b054a4
gcc/ChangeLog diff | blob | blame | history
gcc/config/tilegx/tilegx.c diff | blob | blame | history
gcc/config/tilepro/tilepro.c diff | blob | blame | history
Mirror of https://gcc.gnu.org/git/gcc.git