]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Add combine optimization by slideup for vec_init vectorization
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Fri, 10 Nov 2023 03:36:51 +0000 (11:36 +0800)
committerPan Li <pan2.li@intel.com>
Fri, 10 Nov 2023 14:11:27 +0000 (22:11 +0800)
commit6aaf72ff533550dad68362e8da308b480a9e0f30
tree04788ae10b75b74bde6171aeb31b0092cf786f31
parent62e6ded7ae8582ade4e56aea10d67b9e942d8026
RISC-V: Add combine optimization by slideup for vec_init vectorization

This patch is a small optimization for vector initialization.
Discovered when I am evaluating benchmarks.

Consider this following case:
void foo3 (int8_t *out, int8_t x, int8_t y)
{
  v16qi v = {y, y, y, y, y, y, y, x, x, x, x, x, x, x, x, x};
  *(v16qi*)out = v;
}

Before this patch:

        vsetivli        zero,16,e8,m1,ta,ma
        vmv.v.x v1,a2
        vslide1down.vx  v1,v1,a1
        vslide1down.vx  v1,v1,a1
        vslide1down.vx  v1,v1,a1
        vslide1down.vx  v1,v1,a1
        vslide1down.vx  v1,v1,a1
        vslide1down.vx  v1,v1,a1
        vslide1down.vx  v1,v1,a1
        vslide1down.vx  v1,v1,a1
        vslide1down.vx  v1,v1,a1
        vse8.v  v1,0(a0)
        ret

After this patch:

vsetivli zero,16,e8,m1,ta,ma
vmv.v.x v1,a1
vmv.v.x v2,a2
vslideup.vi v1,v2,8
vse8.v v1,0(a0)
ret

gcc/ChangeLog:

* config/riscv/riscv-protos.h (enum insn_type): New enum.
* config/riscv/riscv-v.cc
(rvv_builder::combine_sequence_use_slideup_profitable_p): New function.
(expand_vector_init_slideup_combine_sequence): Ditto.
(expand_vec_init): Add slideup combine optimization.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/vls/def.h: Add combine test.
* gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/combine-1.c: New test.
* gcc.target/riscv/rvv/autovec/vls/combine-2.c: New test.
* gcc.target/riscv/rvv/autovec/vls/combine-3.c: New test.
* gcc.target/riscv/rvv/autovec/vls/combine-4.c: New test.
* gcc.target/riscv/rvv/autovec/vls/combine-5.c: New test.
* gcc.target/riscv/rvv/autovec/vls/combine-6.c: New test.
* gcc.target/riscv/rvv/autovec/vls/combine-7.c: New test.
gcc/config/riscv/riscv-protos.h
gcc/config/riscv/riscv-v.cc
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/combine-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-1.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-2.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-3.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-4.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-5.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-6.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/combine-7.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h