]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296]
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Wed, 6 Sep 2023 14:28:03 +0000 (22:28 +0800)
committerPan Li <pan2.li@intel.com>
Wed, 6 Sep 2023 14:31:10 +0000 (22:31 +0800)
commit6b96de22d6bcadb45530c1898b264e4738afa4fd
tree7c207f438429dc230b6583f1b0821cebc7be957b
parent1b4c70d4271a00514ae20970d483c3b78d9d66ef
RISC-V: Fix incorrect mode tieable which cause ICE in RA[PR111296]

This patch fix incorrect mode tieable between DI and V2SI which cause ICE
in RA.

gcc/ChangeLog:

PR target/111296
* config/riscv/riscv.cc (riscv_modes_tieable_p): Fix incorrect mode
tieable for RVV modes.

gcc/testsuite/ChangeLog:

PR target/111296
* g++.target/riscv/rvv/base/pr111296.C: New test.
gcc/config/riscv/riscv.cc
gcc/testsuite/g++.target/riscv/rvv/base/pr111296.C [new file with mode: 0644]