]> git.ipfire.org Git - thirdparty/gcc.git/commit
RISC-V: Include pattern stmts for dynamic LMUL computation [PR114516].
authorRobin Dapp <rdapp@ventanamicro.com>
Fri, 21 Feb 2025 16:08:16 +0000 (17:08 +0100)
committerRobin Dapp <rdapp@ventanamicro.com>
Mon, 24 Feb 2025 15:04:13 +0000 (16:04 +0100)
commit6be1b9e94d9a2ead15e3625e833f1e34503ab803
tree03a4b260b1584d0b5ef33f556157f635622b5ebf
parentf3d4208e798afafcba5246334004e9646e390681
RISC-V: Include pattern stmts for dynamic LMUL computation [PR114516].

When scanning for program points, i.e. vector statements, we're missing
pattern statements.  In PR114516 this becomes obvious as we choose
LMUL=8 assuming there are only three statements but the divmod pattern
adds another three.  Those push us beyond four registers so we need to
switch to LMUL=4.

This patch adds pattern statements to the program points which helps
calculate a better register pressure estimate.

PR target/114516

gcc/ChangeLog:

* config/riscv/riscv-vector-costs.cc (compute_estimated_lmul):
Add pattern statements to program points.

gcc/testsuite/ChangeLog:

* gcc.dg/vect/costmodel/riscv/rvv/pr114516.c: New test.
gcc/config/riscv/riscv-vector-costs.cc
gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr114516.c [new file with mode: 0644]