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(parent: f84e4fb) | patch
RISC-V: Support (set (mem) (const_poly_int))
authorJu-Zhe Zhong <juzhe.zhong@rivai.ai>
Mon, 24 Oct 2022 02:03:12 +0000 (10:03 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Mon, 24 Oct 2022 02:31:06 +0000 (10:31 +0800)
commit6bfea64164c3f1989d34656ab96d03a7cda2143e
tree60ba85c8451b9fbd21889ba505efa09c0c0c33a4tree
parentf84e4fb44aa26b71fbc64e0532fd24d96e5caa3fcommit | diff
RISC-V: Support (set (mem) (const_poly_int))

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)).
gcc/config/riscv/riscv.cc diff | blob | blame | history
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