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tests/tcg/hexagon: Add cs{0,1} coverage
authorBrian Cain <brian.cain@oss.qualcomm.com>
Wed, 8 Oct 2025 01:04:53 +0000 (20:04 -0500)
committerBrian Cain <brian.cain@oss.qualcomm.com>
Fri, 17 Oct 2025 20:45:46 +0000 (13:45 -0700)
commit6f6edad6c8daae1e7217ba0066b9e4791187c969
tree63cf018c75f4accdc66eebab0e46e5c519443592tree | snapshot
parent81c9311296ebf67f3821f347141a11838aa7d9d3commit | diff
tests/tcg/hexagon: Add cs{0,1} coverage

Cover cs0,1 register corruption in the signal_context test case.

lc0, sa0 registers previously omitted from the clobbers list
are now captured.

Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
tests/tcg/hexagon/signal_context.c diff | blob | blame | history
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