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(parent: 98d207c) | patch
target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
authorPhilippe Mathieu-Daudé <f4bug@amsat.org>
Fri, 13 Aug 2021 10:36:46 +0000 (12:36 +0200)
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>
Wed, 25 Aug 2021 11:02:14 +0000 (13:02 +0200)
commit71ed30b7d4c7bc7d8069eba601d7384e378f3024
tree9865c4c2e45c54286a3e87dfbc34535a104e8cf7tree | snapshot
parent98d207cf9c232e6ac451b2aba24baa007956f578commit | diff
target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr

Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.

Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-3-f4bug@amsat.org>
target/mips/cpu-defs.c.inc diff | blob | blame | history
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