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target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions
authorSiarhei Volkau <lis8215@gmail.com>
Thu, 8 Jun 2023 10:41:52 +0000 (13:41 +0300)
committerPhilippe Mathieu-Daudé <philmd@linaro.org>
Mon, 10 Jul 2023 21:33:38 +0000 (23:33 +0200)
commit73c260c1a63cabe81676a28e957df10ea2395443
treefb2ff4420f9d3d9bdb4d7521fa252ad67e0921fbtree
parent1980fa0a58ec8deada197e399a1c3c3b78c39e09commit | diff
target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructions

These instructions used to load from memory to GPR via indexed address
divided by base and index parts in GPR registers.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-4-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/mips/tcg/mxu_translate.c diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git