RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

RISC-V: Add testcases for unsigned .SAT_ADD vector form 6

After the middle-end support the form 6 of unsigned SAT_ADD and
the RISC-V backend implement the .SAT_ADD for vector mode, add
more test case to cover the form 6.

Form 6:
  #define DEF_VEC_SAT_U_ADD_FMT_6(T)                                   \
  void __attribute__((noinline))                                       \
  vec_sat_u_add_##T##_fmt_6 (T *out, T *op_1, T *op_2, unsigned limit) \
  {                                                                    \
    unsigned i;                                                        \
    for (i = 0; i < limit; i++)                                        \
      {                                                                \
        T x = op_1[i];                                                 \
        T y = op_2[i];                                                 \
        out[i] = x <= (T)(x + y) ? (x + y) : -1;                       \
      }                                                                \
  }

Passed the rv64gcv regression tests.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_arith.h: Add helper
	macro for testing.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-21.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-22.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-23.c: New test.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-run-24.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>