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git.ipfire.org Git - thirdparty/binutils-gdb.git/commit
RISC-V:[gprofng] Minimal support gprofng for riscv.
ChangeLog: Add target riscv to --enable-gprofng.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* configure: Add riscv.
* configure.ac: Add riscv.
gprofng/ChangeLog: Minimal support gprofng for riscv.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.
(defined): Add riscv.
* gprofng/common/cpuid.c (defined): Add risc-v hwprobe.
* gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.
(defined): Add riscv.
(ARCH_RISCV): Add riscv.
* gprofng/common/hwc_cpus.h: Add RISC-V vendor.
* gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.
* gprofng/configure: Add riscv.
* gprofng/configure.ac: Add riscv.
* gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.
(CONTEXT_PC): Add RISC-V register.
(CONTEXT_FP): Add RISC-V register.
(CONTEXT_SP): Add RISC-V register.
(SETFUNCTIONCONTEXT):
* gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.
* gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.
* gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.
(GET_PC): Add RISC-V register.
(GET_SP): Add RISC-V register.
(GET_FP): Add RISC-V register.
(FILL_CONTEXT):
* gprofng/src/DbeSession.cc (ARCH): Add RISC-V.
* gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.
* gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.
* gprofng/src/checks.cc (ARCH): Add RISC-V.
* gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.
(read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content.
* gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.
19 files changed: