]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commit
RISC-V:[gprofng] Minimal support gprofng for riscv.
authorYixuan Chen <chenyixuan@iscas.ac.cn>
Thu, 4 Jul 2024 09:16:59 +0000 (17:16 +0800)
committerVladimir Mezentsev <vladimir.mezentsev@oracle.com>
Wed, 10 Jul 2024 22:16:03 +0000 (15:16 -0700)
commit762c38d552abbfed97c349c5e7c8ef34119b2f5e
treef0b1d2e5cf0b78204d6ab4d0f8c7dd8c9512a5b7
parent479edf0a6a61159486f14d5e62403f8769cc591d
RISC-V:[gprofng] Minimal support gprofng for riscv.

ChangeLog: Add target riscv to --enable-gprofng.

2024-07-04  Yixuan Chen  <chenyixuan@iscas.ac.cn>

        * configure: Add riscv.
        * configure.ac: Add riscv.

gprofng/ChangeLog: Minimal support gprofng for riscv.

2024-07-04  Yixuan Chen  <chenyixuan@iscas.ac.cn>

        * gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.
        (defined): Add riscv.
        * gprofng/common/cpuid.c (defined): Add risc-v hwprobe.
        * gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.
        (defined): Add riscv.
        (ARCH_RISCV): Add riscv.
        * gprofng/common/hwc_cpus.h: Add RISC-V vendor.
        * gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.
        * gprofng/configure: Add riscv.
        * gprofng/configure.ac: Add riscv.
        * gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.
        (CONTEXT_PC): Add RISC-V register.
        (CONTEXT_FP): Add RISC-V register.
        (CONTEXT_SP): Add RISC-V register.
        (SETFUNCTIONCONTEXT):
        * gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.
        * gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.
        * gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.
        (GET_PC): Add RISC-V register.
        (GET_SP): Add RISC-V register.
        (GET_FP): Add RISC-V register.
        (FILL_CONTEXT):
        * gprofng/src/DbeSession.cc (ARCH): Add RISC-V.
        * gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.
        * gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.
        * gprofng/src/checks.cc (ARCH): Add RISC-V.
        * gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.
        (read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content.
        * gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.
19 files changed:
configure
configure.ac
gprofng/common/core_pcbe.c
gprofng/common/cpuid.c
gprofng/common/gp-defs.h
gprofng/common/hwc_cpus.h
gprofng/common/hwcfuncs.h
gprofng/configure
gprofng/configure.ac
gprofng/libcollector/hwprofile.h
gprofng/libcollector/libcol_util.c
gprofng/libcollector/libcol_util.h
gprofng/libcollector/unwind.c
gprofng/src/DbeSession.cc
gprofng/src/Disasm.cc
gprofng/src/Experiment.cc
gprofng/src/checks.cc
gprofng/src/collctrl.cc
gprofng/src/dbe_types.h