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target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB
authorRichard Henderson <richard.henderson@linaro.org>
Tue, 28 May 2024 20:30:13 +0000 (13:30 -0700)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 30 May 2024 14:24:38 +0000 (15:24 +0100)
commit76f4a8aecae7f287d6e7f3b763ae88382c3a5457
treea12f9fc1acf4b07db71013b09f9078f84fdb8918tree
parentb1d592e7b0a7301eae8e3baa99744ac35db3cd2acommit | diff
target/arm: Improve vector UQADD, UQSUB, SQADD, SQSUB

No need for a full comparison; xor produces non-zero bits
for QC just fine.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240528203044.612851-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/tcg/gengvec.c diff | blob | blame | history
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