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(parent: 9e946ea) | patch
target/arm: Flush high bits of sve register after AdvSIMD EXT
authorRichard Henderson <richard.henderson@linaro.org>
Fri, 14 Feb 2020 19:46:40 +0000 (11:46 -0800)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 21 Feb 2020 16:07:00 +0000 (16:07 +0000)
commit78cedfabd53b6f64e7e64fc84878d848e5df1d08
tree71dc8e562872b79199cdf2f032664a0c2db93f0atree | snapshot
parent9e946eaba87916c43aaf0b2760bd5d5a54187c7bcommit | diff
target/arm: Flush high bits of sve register after AdvSIMD EXT

Writes to AdvSIMD registers flush the bits above 128.

Buglink: https://bugs.launchpad.net/bugs/1863247
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214194643.23317-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/translate-a64.c diff | blob | blame | history
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