target/riscv: Fix the rvv reserved encoding of unmasked instructions

target/riscv: Fix the rvv reserved encoding of unmasked instructions

According to the v spec, the encodings of vcomoress.vm and vector
mask-register logical instructions with vm=0 are reserved.

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-11-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
(cherry picked from commit 8539a1244bf240d28917effb88a140eb58e45e88)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>