RISC-V: Refine the rtl expand check for strided ld/st

RISC-V: Refine the rtl expand check for strided ld/st

This patch would like to remove the unnecessary option for the
strided load/store testcases.  After fix the option from the rvv.exp,
both the O2 and O3 will be passed to the test files for rtl expand
dump check but the O2 has 2 time for IFN while the O3 has 4 times with
-fvectorize specificed.

Thus, add xfail O2 for IFN 4 times check, as well as xfail O3 for 2
times check.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Remove
	unnecessary optimization option and xfail O2/O3 diff IFN times
	from the rtl expand dump.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>