[RISC-V] [V2] [PR target/116715] Remove bogus bitmanip pattern

[RISC-V] [V2] [PR target/116715] Remove bogus bitmanip pattern

So for this bug we have what appears to me to just be a bogus pattern.

Essentially the pattern tries to detect cases where we have an SI mode value
and we can use the Zbs instructions to manipulate a bit. Conceptually that's
great.

The problem is the pattern assumes that SI objects are sign extended. It uses a
test to try and filter out a problematical case (subregs), but that simply
won't work with late-combine since the subreg will be stripped away and we have
no way of knowing if the SI value was already sign extended to 64 bits or not.

You might think we could look for a way to salvage the pattern and make it only
usable prior to register allocation.  I pondered that extensively, but
ultimately concluded that with the introduction of ext-dce it wasn't safe.

So this just removes the problematical pattern.  Thankfully there aren't any
regressions in the testsuite.  Even the test designed to test this pattern's
applicability still generates the desired code.

Changes since v1:
  - Adjust testcase so that it works for rv32 and rv64.
  - Adjust PR number in subject line.

	PR target/116715
gcc/
	* config/riscv/bitmanip.md: Drop bogus pattern.

gcc/testsuite
	* gcc.target/riscv/pr116715.c: New test.