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[riscv] Add fences around early UART writes
authorMichael Brown <mcb30@ipxe.org>
Mon, 2 Jun 2025 07:36:22 +0000 (08:36 +0100)
committerMichael Brown <mcb30@ipxe.org>
Mon, 2 Jun 2025 07:36:22 +0000 (08:36 +0100)
commit7df005c4c6fa0300f7bfe54e184bc5291bb742af
tree000a821c8aa2f97a9665d77a7f4fbc9636841b0btree | snapshot
parent88cffd75a9c2cc15780d465fe4e9ccf45719d6c9commit | diff
[riscv] Add fences around early UART writes

Add a fence between the write to the UART transmit register and the
subsequent read from the transmit status register, to ensure that the
status correctly reflects the occurrence of the write.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
src/arch/riscv/prefix/libprefix.S diff | blob | blame | history
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