RISC-V: RVV: add toggle to control vsetvl pass behavior

RISC-V: RVV: add toggle to control vsetvl pass behavior

RVV requires VSET?VL? instructions to dynamically configure VLEN at
runtime. There's a custom pass to do that which has a simple mode
which generates a VSETVL for each V insn and a lazy/optimal mode which
uses LCM dataflow to move VSETVL around, identify/delete the redundant
ones.

Currently simple mode is default for !optimize invocations while lazy
mode being the default.

This patch allows simple mode to be forced via a toggle independent of
the optimization level. A lot of gcc developers are currently doing this
in some form in their local setups, as in the initial phase of autovec
development issues are expected. It makes sense to provide this facility
upstream. It could potentially also be used by distro builder for any
quick workarounds in autovec bugs of future.

gcc/ChangeLog:
	* config/riscv/riscv.opt: New -param=vsetvl-strategy.
	* config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
	* config/riscv/riscv-vsetvl.cc
	(pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
	(pass_vsetvl::execute): Use vsetvl_strategy.

Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>