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RISC-V: Fix typos on comments (SVE -> RVV)
authorTsukasa OI <research_trasio@irq.a4lg.com>
Tue, 19 Sep 2023 02:10:31 +0000 (02:10 +0000)
committerTsukasa OI <research_trasio@irq.a4lg.com>
Tue, 19 Sep 2023 02:46:10 +0000 (02:46 +0000)
commit7f4fc87086b5ad57edaaf628ba6cb92649d14453
tree945e551c066f487a90add6645e228b7a70153factree
parentf45cca26263c3563e9db15e0ba64d4a114316808commit | diff
RISC-V: Fix typos on comments (SVE -> RVV)

We have the 'V' extension (RVV), not SVE from AArch64.

gcc/ChangeLog:

* config/riscv/riscv-vector-builtins.cc
(builtin_decl, expand_builtin): Replace SVE with RVV.
gcc/config/riscv/riscv-vector-builtins.cc diff | blob | blame | history
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