RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API

This patch support the intrinsic API of FP16 ZVFHMIN vlmul ext. Aka:

vfloat16*_t <==> vfloat16*_t.

From the user's perspective, it is reasonable to do some type convert
between vfloat16*_t and vfloat16*_t when only ZVFHMIN is enabled.

Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:

	* config/riscv/riscv-vector-builtins-types.def
	(vfloat16mf4_t): Add type to X2/X4/X8/X16/X32 vlmul ext ops.
	(vfloat16mf2_t): Ditto.
	(vfloat16m1_t): Ditto.
	(vfloat16m2_t): Ditto.
	(vfloat16m4_t): Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Add new test cases.
	* gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Add new test cases.