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(parent: dfa9c2a) | patch
target-mips: Correct the handling of register #72 on writes
authorMaciej W. Rozycki <macro@codesourcery.com>
Mon, 3 Nov 2014 18:47:45 +0000 (18:47 +0000)
committerLeon Alrae <leon.alrae@imgtec.com>
Tue, 16 Dec 2014 12:45:19 +0000 (12:45 +0000)
commit800675f11742b6080e40d17b8d5f35d3a5fc5724
tree4c045b49cd4895afa41cecfc2ff3304fc1096f1etree
parentdfa9c2a0f4d0a0c8b2c1449ecdbb1297427e1560commit | diff
target-mips: Correct the handling of register #72 on writes

Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
matching how `mips_cpu_gdb_read_register' handles it.  This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips/gdbstub.c diff | blob | blame | history
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