RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688]

RISC-V: Fix incorrect code gen for scalar signed SAT_ADD [PR117688]

This patch would like to fix the wroing code generation for the scalar
signed SAT_ADD.  The input can be QI/HI/SI/DI while the alu like sub
can only work on Xmode.  Unfortunately we don't have sub/add for
non-Xmode like QImode in scalar, thus we need to sign extend to Xmode
to ensure we have the correct value before ALU like add.  The gen_lowpart
will generate something like lbu which has all zero for highest bits.

For example, when 0xff(-1 for QImode) plus 0x2(1 for QImode), we actually
want to -1 + 2 = 1, but if there is no sign extend like lbu, we will get
0xff + 2 = 0x101 which is incorrect.  Thus, we have to sign extend 0xff(Qmode)
to 0xffffffffffffffff(assume XImode is DImode) before plus in Xmode.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

	PR target/117688

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_expand_ssadd): Leverage the helper
	riscv_extend_to_xmode_reg with SIGN_EXTEND.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/pr117688-add-run-1-s16.c: New test.
	* gcc.target/riscv/pr117688-add-run-1-s32.c: New test.
	* gcc.target/riscv/pr117688-add-run-1-s64.c: New test.
	* gcc.target/riscv/pr117688-add-run-1-s8.c: New test.
	* gcc.target/riscv/pr117688.h: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>