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(parent: e8d41e0) | patch
RISC-V: Add ZVFHMIN block autovec testcase
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Mon, 12 Jun 2023 09:44:58 +0000 (17:44 +0800)
committerPan Li <pan2.li@intel.com>
Mon, 12 Jun 2023 12:23:13 +0000 (20:23 +0800)
commit84cbf560ff62a57432374d8a878251234ffcb99a
tree05f903db1d719cf6a153a1b69ebe852be448f030tree
parente8d41e031b9f52601249ec7e4c4215b851cc8ffecommit | diff
RISC-V: Add ZVFHMIN block autovec testcase

To be safe, add ZVFHMIN autovec block testcase to make sure
we won't enable autovec in ZVFHMIN by mistakes.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/zvfhmin-1.c: New test.
gcc/testsuite/gcc.target/riscv/rvv/autovec/zvfhmin-1.c [new file with mode: 0644] blob
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